The present invention relates to a microprocessor having an improved method for retrying a data transfer cycle.
A microprocessor of this type is disclosed in U.S. Pat. 4,348,722. In this microprocessor, a normal end signal (DTACK) as well as an abnormal end signal (BERR) and a retry request signal (HALT) are used as data transfer response signals in order to retry a data transfer cycle.
FIGS. 1 and 5B of the U.S. Pat. 4,348,722 are quoted in FIGS. 7 and 8. As shown in FIG. 8, when the data transfer ends abnormally and the retry is requested, the signals BERR and HALT are asserted.
In requesting the retry, the following items must be checked:
(1) Whether the number of times of retry exceeds a limit?
(2) Whether the data transfer is retryable? That is, whether access to a control register is included?
(3) Whether the retry is significant? That is, whether access to an unmounted area is included?
The retry cannot be requested unless the above items have been checked.
In the prior art, timing of the BERR and HALT signal generation circuit is critical and it is difficult to design an external circuit of the microprocessor.